In this example counting advances on
the falling-edge of the clock signal
LED on = 1 LED off = 0
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Also See: 4000 series ICs | 74 series ICs |
Logic Gates
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Counting one, two, three, four, five in binary: 1, 10, 11, 100, 101.
Binary numbers rapidly become very long as the count increases and this makes them difficult for us to read at a glance. Fortunately it is rarely necessary to read more than 4 binary digits at a time in counting circuits.
In a binary number each digit represents a multiple of two (1, 2, 4, 8, 16 etc), in the same way that
each digit in decimal represents a multiple of ten (1, 10, 100, 1000 etc).
For example 10110110 in binary equals 182 in decimal:
| Digit value: | 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1 | |||||||||
| Binary number: | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | |||||||||
| Decimal value: | 128 | + | 0 | + | 32 | + | 16 | + | 0 | + | 4 | + | 2 | + | 0 | = | 182 |
A block of 8 bits is called a byte and it can hold a maximum number of 11111111 = 255 in decimal. Computers and PIC microcontrollers work with blocks of 8 bits. Two (or more) bytes make a word, for example PICs work with a 16-bit word (two bytes) which can hold a maximum number of 65535.
A block of 4 bits is called a nibble (half a byte!) and it can hold a maximum number of 1111 = 15 in decimal. Many counting circuits work with blocks of 4 bits because this number of bits is required to count up to 9 in decimal. (The maximum number with 3 bits is only 7).
Example: 10110110 binary = B6 hexadecimal = 182 decimal.
| Binary D C B A |
Decimal | Hex base 16 |
| 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 |
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
0 1 2 3 4 5 6 7 8 9 A B C D E F |
The labels A,B,C,D are widely used in electronics to represent the four bits:
Several decade counters using BCD can be linked together to separately count the decimal ones, tens, hundreds, and so on. This is much easier than attempting to convert large binary numbers (such as 10110110) to display their decimal value.
Do not confuse BCD which stands for Binary Coded Decimal with the labels A,B,C,D used to represent
the four binary digits; it is an unfortunate coincidence that the letters BCD occur in both!
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| A square wave clock signal |
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| The bouncing output from a switch |
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| A 4-bit counter and clock input In this example counting advances on the falling-edge of the clock signal LED on = 1 LED off = 0 |
Most switches bounce when the contacts close giving a rapid series of pulses. Connecting a switch directly to a clock input will usually give several counts when the switch is operated once! One way to 'debounce' the switch is to make it trigger a 555 monostable circuit with a short time period (such as 0.1s) and use the monostable output to drive the clock input.
The animated block diagram shows a clock signal driving a 4-bit (0-15) counter with LEDs connected to show the state of the clock and counter outputs QA-QD (Q indicates an output).
The LED on the first output QA flashes at half the frequency of the clock LED. In fact the frequency of each stage of the counter is half the frequency of the previous stage. You can see this pattern too in the table above showing the 4-bit numbers.
Notice how output QA changes state every time the clock input changes from high to low (that is when the clock LED turns off), this is called the falling-edge. If you watch the counting closely you can see that QB changes on the falling-edge of QA, QC on the falling-edge of QB and so on.
You may be surprised to see the diagram drawn with the input on the right and signals
flowing from right to left, the opposite way to the usual convention in electronics!
Drawing counter circuits like this means that the outputs are in the correct binary order for us
to read easily and I think this is more helpful than rigidly sticking to the usual 'left to right'
convention.
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| The operation of a flip-flop Notice how the output frequency is half the input frequency |
A ripple counter contains a chain of flip-flops with the output of each one feeding the input of the next. A flip-flop output changes state every time the input changes from high to low (on the falling-edge). This simple arrangement works well, but there is a slight delay as the effect of the clock 'ripples' through the chain of flip-flops.
In most circuits the ripple delay is not a problem because it is far too short to be seen on a display. However, a logic system connected to ripple counter outputs will briefly see false counts which may produce 'glitches' in the logic system and may disrupt its operation. For example a ripple counter changing from 0111 (7) to 1000 (8) will very briefly show 0110, 0100 and 0000 before 1000!
A synchronous counter has a more complex internal structure to ensure that all its outputs change
precisely together on each clock pulse, avoiding the brief false counts which occur with ripple counters.
Counting occurs when the clock input changes state.
Counters can be reset to zero before their maximum count by connecting one (or more) of their outputs to their
reset input, using an AND gate to combine outputs if necessary.
If the reset input is 'active-low' a NOT or NAND gate will be required to produce a low output
at the desired count. If you see a line drawn above reset it means it is active low, for example:
(say 'reset-bar').
The reset function normally occurs immediately and you should reset on the next count above the maximum you require. For example to count 0-5 (0000-0101) you should reset on 6 (0110).
Some synchronous counters have a synchronous reset which occurs on the next clock pulse rather than immediately. This is important because you must reset on the maximum count you require. For example to count 0-5 (0000-0101), reset on 5 (0101).
Frequency division is one of the main purposes of counters with more than 4 bits and their outputs are
usually labelled Q1, Q2 and so on. Qn is the nth stage of the counter, representing 2n.
For example Q4 is 24 = 16 (1/16 of clock
frequency) and Q12 is 212 = 4096 (1/4096
of clock frequency).
The most popular type is a 1-of-10 decoder which contains a network of logic gates to make
one of its ten outputs Q0-9 become high (or low) in response to the BCD (binary coded decimal)
inputs A-D. For example an input of binary 0101 (=5) will activate output Q5.
Decoders can be used for a simple counting display and for switching LEDs in sequences. The outputs must never be directly connected together, but diodes can be used to combine them as shown in the diagram.
For example using diodes to combine the 2nd (Q1) and 4th (Q3) outputs will make an LED flash twice
followed by a longer gap. The top diagram shows this for a decoder where the outputs become
low when activated (such as the 7442),
and the bottom diagram for a decoder where the outputs become high when activated (such as the
4028).
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| Decade counter with display driver and 7-segment display |
is a suitable value for many
displays with a 4.5V to 6V supply.
Beware that these resistors are sometimes omitted from circuit diagrams!
There are two types of 7-segment displays:
Some dual counter ICs are available with two separate counters on the same IC, the two counters must be linked externally if required (there is no internal link).
The way that counters are linked depends on the nature of the counter. The diagrams below show the general arrangements for standard ripple and synchronous counters but it is important to read the detailed information for particular counters, consulting a datasheet if necessary.
Remember that with all ripple counters there will be a slight delay before the later outputs respond
to the clock signal, especially with a long counter chain. This is not a problem in simple circuits
driving displays, but it may cause glitches in logic systems connected to the counter outputs.
